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preliminary data sheet september 2001 l7585f full-feature, low-power slic and switch features low active power quiet tip/ring polarity reversal distortion-free on-hook transmission 35 v to 60 v power supply operation 14 operating states: ? forward battery active ? reverse battery active ? ground start (3) ? forward battery ring open ? reverse battery ring open ? reverse battery tip open ? high impedance ? ringing (2) ? low current (2) ? disconnect self-test in all operating states independent, adjustable ac and dc parameters: ? switchhook detector threshold ? loop current limit ? dc feed resistance ? termination impedance integrated ringing access relay integrated test-in relay integrated relay driver integrated ring trip detector thermal protection 44-pin, surface-mount, plastic package (plcc) description the l7585f full-feature, low-power subscriber loop interface circuit (slic) and switch integrates the battery feed, test access relay, and ringing relay that are necessary to interface a codec to the tip and ring of a subscriber loop into one low-power, low-cost package. it is built using a 90 v complementary bipolar (cbic) process and a 320 v bipolar-cmos-dmos (bcdmos) process. the device is available in a 44-pin plcc package. the device can be connected directly to the agere systems inc. t8531/t8532 16-channel programmable codec chip set without the need for any ac interface components.
2 data sheet september 2001 l7585f full-feature, low-power slic and switch table of contents contents page features.................................................................................1 description ...........................................................................1 architectural diagram ..........................................................3 pin information.....................................................................4 operating states....................................................................7 forward battery active state ............................................7 ground start/tip open state .............................................7 ground start/tip ground state..........................................8 forward battery ring open state......................................8 ringing states (2) ..............................................................8 disconnect state ................................................................8 forward battery low-current active state ......................8 high-impedance states (2) ................................................8 reverse battery active state .............................................8 reverse battery tip open state ........................................8 ground start/tip amplifier state ......................................9 reverse battery ring open state ......................................9 reverse battery low-current active state .......................9 absolute maximum ratings (t a = 25 c) ...........................9 electrical characteristics ....................................................10 on-state switch v-i characteristics ..................................17 applications........................................................................18 tip/ring protection .........................................................18 ndet under fault conditions........................................18 power, clocking, and layout ..........................................18 ring trip..........................................................................19 false on-hook transients ...............................................19 application diagram ..........................................................20 outline diagram .................................................................21 44-pin plcc....................................................................21 ordering information .........................................................22 figures page figure 1. architectural diagram ......................................... 3 figure 2. 44-pin diagram (plcc) ...................................... 4 figure 3. on-state switch v-i characteristics .................. 17 figure 4. 16-channel line card solution ......................... 20 tables page table 1. pin descriptions .................................................... 5 table 2. b0?b3 input state coding ................................... 7 table 3. b4?b5 input state coding ................................... 7 table 4. operating conditions and powering ................... 10 table 5. ring trip detector .............................................. 10 table 6. battery feed characteristics ............................... 11 table 7. analog signal pins .............................................. 12 table 8. transmission characteristics .............................. 13 table 9. data interface and logic (logic inputs [clk, ncs, and b0?b5] and outputs [ndet]) ............................................... 14 table 10. timing requirements (clk, b0?b5, and ncs) ......................................................... 14 table 11. relay driver (rdo) .......................................... 14 table 12. ringing return access switch (sw1) .............. 15 table 13. test-in access switches (sw3 and sw6) ............................................... 15 table 14. tip and ring break switches (sw2 and sw4) ............................................... 16 table 15. tip and ring feedback switches (sw2a and sw4a) ........................................... 16 table 16. ringing access switch (sw5) .......................... 17
3 data sheet september 2001 l7585f full-feature, low-power slic and switch architectural diagram 12-3290.e(f) figure 1. architectural diagram rft 20 ? tip/ring current sense rfr 20 ? v bat v bat npdat npdar trng tti pt pr rti ring trip detector sw5 rd relay driver nrt rsw rts rrng dc feedback and current limit dc out ac interface v bat buffer buffer rdo dgnd v ccd v sp i prog dcr cf2 cf1 v bat bgnd buffer buffer ac dc v bat fb2 fb1 rcvn rcvp ar + ? 75 a parallel data latch and logic switchhook detector ncsb5b4 b3b2b1 b0 clk ndet rd fb nrt nlc sw1?sw6 control +? agnd v cca sw1 45 ? lcth dc out vrtx vtx 2.4 v reference txi vitr itr aac ref in rectifier gain = 3 out ax + ? 50 a +5 a itr itr at ? + +5 a npdat npdar fb 100 k ? itr/198 sw3 45 ? gto +5 a +5 d +10 v sw6 sw4 sw4a sw2a 4 k ? sw2 25 ?
4 data sheet september 2001 l7585f full-feature, low-power slic and switch pin information 12-2571(f).f figure 2. 44-pin diagram (plcc) i prog dgnd v ccd b0 b1 b2 bgnd fb1 fb2 v bat v sp ncs ndet dgnd 7 9 10 11 12 13 14 15 16 17 8 6 4 3 2 1 4443424140 5 18 20 21 22 23 24 25 26 27 28 19 39 37 36 35 34 33 32 31 30 29 38 v bat b3 v bat bgnd itr vitr txi cf1 clk agnd v cca rcvn rcvp vrtx lcth vtx dc out dcr cf2 b4 trng rts pr b5 pt tti rti rrng rsw rdo
5 data sheet september 2001 l7585f full-feature, low-power slic and switch pin information (continued) table 1. pin descriptions note: on the printed-wiring board (pwb), make the leads to bgnd and v bat as wide as possible for thermal and electrical reasons. also, maximize the amount of pwb copper on all leads connected to this device for the lowest operating temperature. pin symbol type name/function 1v cca ? +5 v analog dc supply. +5 v supply for analog circuitry. 2 lcth i loop closure threshold input. connect a resistor to dc out to set the off-hook threshold. 3 i prog i current-limit program input. a resistor to dc out sets the dc current limit. 4 dc out o dc output. this output is a voltage that is directly proportional to the differential tip/ring current. 5 dcr i dc resistance. ground for dc feed resistance of 180 ? , or short to dc out for 600 ? . intermediate values can be set with a resistor divider from dc out to ground, the tap of which is connected to dcr. 6 cf2 i/o filter capacitor 2. connect a 0.1 f, 100 v capacitor from this pin to agnd and a 0.22 f, 100 v capacitor from this pin to pin cf1. 7 cf1 i/o filter capacitor 1. connect a 0.22 f, 100 v capacitor from this pin to pin cf2. 8 fb2 i forward battery slowdown 2. a capacitor from fb1 to agnd and from fb2 to agnd will ramp the polarity reversal transition when quiet polarity reversal is required. if not needed, the pin can be left open. 9 fb1 i forward battery slowdown 1. a capacitor from fb1 to agnd and from fb2 to agnd will ramp the polarity reversal transition when quiet polarity reversal is required. if not needed, the pin can be left open. 10 bgnd ? battery ground. ground return for the battery (v bat ) supply. 11 v bat ? battery supply. negative high-voltage power supply. 12 v bat ? battery supply. negative high-voltage power supply. 13 v sp ? +10 v supply. +10 v bias supply for switch circuitry. 14 ncs i not channel select. a low-to-high transition on this logic input stores the data on pins b0?b5 into the input latches on the slic. when ncs is either high or low, the slic is unaffected by data on pins b0?b5. 15 clk i clock. clock input. 16 ndet o not detect. when low, this logic output indicates either a ring trip or an off-hook condition, de- pending on the input state of the slic. if either the bcdmos portion or cbic portion of this de- vice enters thermal shutdown, ndet will be forced low. 17 dgnd ? digital ground. ground return for v ccd and relay driver flyback current. 18 rdo o relay driver. this output drives an external relay. rdo is low (relay operated) when a low input on b5 is latched into the slic. 19 rts i ring trip sense. sense input for the ring trip detector. 20 rsw o ring lead ringing access switch. ringing relay connects this pin to pin rrng. connect this pin to pin pr through a 500 ? current-limiting resistor. 21 rrng i ring lead ringing supply. connect this pin to the ringing supply. 22 pr i/o protected ring. the output of the ring driver and input to the transmit current sense circuit. con- nect to the ring of the loop through overvoltage protection.
6 data sheet september 2001 l7585f full-feature, low-power slic and switch pin information (continued) table 1. pin descriptions (continued) note: on the printed-wiring board (pwb), make the leads to bgnd and v bat as wide as possible for thermal and electrical reasons. also, maximize the amount of pwb copper on all leads connected to this device for the lowest operating temperature. pin symbol type name/function 23 rti i ring lead test-in. test-in relay connects this pin to pr. connect rti to the ring lead of the test-in bus. 24 tti i tip lead test-in. test-in relay connects this pin to pt. connect tti to the tip lead of the test-in bus. 25 pt i/o protected tip. the output of the tip driver and input to the transmit current sense circuit. connect to the tip of the loop through overvoltage protection. 26 trng o tip lead ringing supply. ringing relay connects this pin to pt. connect trng to the ringing supply return. 27 b5 i bit 5. b0?b5 determine the state of the slic. see operating states. 28 b4 i bit 4. b0?b5 determine the state of the slic. see operating states. 29 b3 i bit 3. b0?b5 determine the state of the slic. see operating states. 30 b2 i bit 2. b0?b5 determine the state of the slic. see operating states. 31 b1 i bit 1. b0?b5 determine the state of the slic. see operating states. 32 b0 i bit 0. b0?b5 determine the state of the slic. see operating states. 33 v ccd ? +5 v digital dc supply. +5 v supply for logic and switch circuitry. 34 dgnd ? digital ground. ground return for v ccd . 35 v bat ? battery supply. negative high-voltage power supply. 36 bgnd ? battery ground. ground return for the battery (v bat ) supply. 37 itr i tip/ring current. a current output which is proportional to the differential current flowing from tip to ring. connect a resistor from this pin to vitr. 38 vitr o tip/ring voltage output. the voltage at this output is directly proportional to the differential tip/ ring current. a resistor from this pin to itr sets the gain. 39 txi i transmit ac input. connect a 0.1 f capacitor from this pin to vitr. 40 vtx o transmit ac output voltage. the ac voltage at this output is 7.2 times the ac voltage at pin txi. the dc voltage is equal to the dc voltage on pin vrtx. 41 vrtx o transmit ac reference voltage. the dc voltage at this output (2.4 v nominal) is the dc reference for the transmit signal output vtx. 42 rcvp i receive ac signal input (noninverting). this high-impedance input controls the ac differential voltage on tip and ring. 43 rcvn i receive ac signal input (inverting). this high-impedance input controls the ac differential volt- age on tip and ring. 44 agnd ? analog ground. ground return for v cca .
7 data sheet september 2001 l7585f full-feature, low-power slic and switch operating states the l7585 has 13 operating states. these states are selected using 4 bits, b0?b3, according to the truth table shown in table 2. the operation of the l7585 is undefined for unas- signed states. additionally, bit b4 independently operates the test-in access contacts so that all states are available for self-test; and bit b5 independently operates a relay driver, regardless of the status of bits b0?b4. all 6 bits are loaded via the parallel data interface and chip select lead ncs. table 2. b0?b3 input state coding table 3. b4?b5 input state coding forward battery active state normal talk and forward battery feed state. all circuits are powered up and active. pin pt is positive with respect to pin pr (forward battery). sw2, sw2a, sw4, and sw4a closed; sw1, sw3, sw5, and sw6 open. ndet reflects the status of the switchhook detector. ground start/tip open state ground start idle supervision state. ring lead continuity test state (tone injected at the receive port) in forward battery. same as forward battery active state, but with sw2 and sw2a open, and the tip drive amplifier powered down. pin pt is high impedance (>100 k ? ). the ring current limit is approximately equal to the value programmed for the high-current active state current limit. current limit is achieved by reducing the ring lead voltage only (see table 6). ndet indicates an off-hook when the ring current (flow- ing into pr) is twice the value programmed for the switch- hook detector in the forward battery active state. b3 b2 b1 b0 state 1 1 1 1 forward battery active 1 1 1 0 ground start/tip open 1 1 0 1 ground start/tip ground 1 1 0 0 forward battery ring open 1 0 1 1 ringing (battery backed) 1 0 1 0 disconnect state 1 0 0 1 forward battery low current ac- tive state 1 0 0 0 high impedance 0 1 1 1 reverse battery active 0 1 1 0 reverse battery tip open 0 1 0 1 ground start/tip amplifier 0 1 0 0 reverse battery ring open 0 0 1 1 ringing (earth backed) 0 0 1 0 unassigned 0 0 0 1 reverse battery low-current ac- tive state 0 0 0 0 high impedance bit state b4 1 test-in contacts off. 0 test-in contacts on. b5 1 relay driver off. 0 relay driver on.
8 8 data sheet september 2001 l7585f full-feature, low-power slic and switch operating states (continued) ground start/tip ground state ground start busy supervision state. same as ground start/tip open state but with sw1 closed. forward battery ring open state tip lead continuity test state (tone injected at the receive port) in forward battery. same as forward battery active state, but with sw4 and sw4a open, and the ring drive amplifier powered down. pin pr is high impedance (>100 k ? ). tip current limit is twice the low-current active state cur- rent limit. ndet indicates an off-hook when the tip current (flowing out of pt) is twice the value programmed for the switch- hook detector in the forward battery active state. ringing states (2) normal ringing state. tip and ring drive amplifiers are powered down. sw1 and sw5 closed; sw2, sw2a, sw3, sw4, sw4a, and sw6 open. ndet reflects the status of the ring trip detector. bit b3 indicates whether the ringing voltage applied to the ringing bus is either battery backed (b3 = 1) or earth backed (b3 = 0). although b3 has no direct effect on the state of the slic, it can be used by the ring trip detector to enhance ring trip detection. disconnect state all circuits are powered up and active. sw2, sw2a, sw4, and sw4a closed; sw1, sw3, sw5, and sw6 open. pt and pr are at the same potential to deny current to the loop. forward battery low-current active state normal talk and forward battery feed state. all circuits are powered up and active. pin pt is positive with respect to pin pr (forward battery). sw2, sw2a, sw4, and sw4a closed; sw1, sw3, sw5, and sw6 open. ndet reflects the status of the switchhook detector. current limit is lowered to approximately 0.66 times the normal limit. high-impedance states (2) disconnect state. tip and ring drive amplifiers are powered down (all bias currents off). pins pt and pr are high impedance (>100 k ? ). sw1, sw2, sw2a, sw3, sw4, sw4a, sw5, and sw6 open. ndet is undefined. reverse battery active state normal talk and reverse battery feed state. same as forward battery active state, but pr is positive with respect to pt. reverse battery tip open state ring lead continuity test state (tone injected at the receive port) in reverse battery. sw2 and sw2a open and the tip drive amplifier powered down. pin pt is high impedance (>100 k ? ). pin pr is held between -1.7 v and -2.3 v for pr currents less than +-20 ma. pr current limit is the sw4 break switch current limit (250 ma < i < 85 ma). ndet indicates an off-hook when the ring current (flow- ing out of pr) is twice the value programmed for the switchhook detector in the reverse battery active state.
9 data sheet september 2001 l7585f full-feature, low-power slic and switch operating states (continued) ground start/tip amplifier state current limiting is achieved by reducing ring lead voltage only. this state is the same as ground start/tip open, but with sw2 and sw2a closed and the tip amplifier pow- ered up. ring lead current limit is approximately the difference of the high-current active state limit and the current flowing out of the tip lead. on-hook transmission not to exceed ?3 dbm with up to 5 ma flowing out of the tip lead (maximum current flow into the tip lead is permissible). larger signal and/or cur- rent may cause distortion. ndet indicates an off-hook when the current flowing out of the tip plus the current flowing into the ring is twice the value programmed for the switchhook detector. reverse battery ring open state tip lead continuity test state (tone injected at the receive port) in reverse battery. same as reverse battery active state, but with sw4 and sw4a open, and the ring drive amplifier powered down. pin pr is high impedance (>100 k ? ). tip current limit is twice the low-current active state cur- rent limit. ndet indicates an off-hook when the tip current (flowing into pt) is twice the value programmed for the switch- hook detector in the reverse battery active state. reverse battery low-current active state normal talk and reverse battery feed state. same as forward battery active state, but pr is positive with respect to pt. current limit is lowered to approximately 0.66 times the normal limit. absolute maximum ratings (t a = 25 c) stresses exceeding the values listed under absolute maxi- mum ratings may cause permanent damage to the device. this is an absolute stress rating only. functional operation of the device at these or any other conditions in excess of those indicated in the operational sections of this data sheet is not implied. exposure to absolute maximum rating conditions for extended periods of time may adversely affect device reliability. note: analog voltages are referenced to agnd, digital (logic) voltages are referenced to dgnd, and battery voltages are referenced to bgnd. the ic can be damaged unless all ground connections are applied before and are removed after all other connections. fur- thermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. some of the known examples of condi- tions that cause such potentials during powering are the following: 1) an inductor connected to tip and ring that can force an overvolt- age on v bat through external components if the v bat connection chatters; and 2) inductance in the v bat lead that could resonate with the v bat filter capacitor to cause a destructive overvoltage. parameter value unit +5 v dc supplies (v cca and v ccd ) ?0.5 to +7.0 v +10 v dc bias supply (v sp )?0.5 to +15v office battery supply (v bat ) ?63 to +0.5 v logic input voltage ?0.5 to v ddd + 0.5 v logic input clamp diode current, per pin 20 ma logic output voltage ?0.5 to v ddd + 0.5 v logic output current, per pin (ex- cluding relay driver) 35 ma operating temperature range ?40 to +125 c storage temperature range ?40 to +125 c relative humidity range 5 to 95 %rh ground potential difference (bgnd to agnd) 3 v ground potential difference (dgnd to agnd) 3 v
10 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics in general, minimum and maximum values are testing requirements. however, some parameters may not be tested in produc- tion because they are guaranteed by design and device characterization. typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. minimum and maximum values apply across the entire temperature range (?40 c to +85 c) and entire battery range (?35 v to ?60 v). unless otherwise specified, typical is defined as 25 c, v cca = +5.0 v, v ccd = +5.0 v, v sp = +10 v, v bat = ?48 v. positive currents flow into the device. * not to exceed 26 grams of water per kilogram of dry air. ? this parameter is not tested in production; it is guaranteed by design and device characterization. 1. the ringing source may be either of the following: a). the ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. in this case, bit b3 will always be a 1 when ringing is applied. b). the ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage. in this cas e, bit b3 will always be a 0 when ringing is applied. 2. ndet must also indicate ring trip when the ac ringing voltage is absent (<5 vrms) from the ringing source. 3. pretrip ringing must not be tripped by a 10 k ? resistor in parallel with an 8 f capacitor applied across tip and ring. table 4. operating conditions and powering parameter min typ max unit temperature range ?40 ? 85 c humidity range 5 ? 95* %rh supply voltages: v cca v ccd v sp v bat v cca ?v ccd d gnd ?a gnd 4.75 4.75 8.0 ?35 ? ? 5.0 5.0 10 ?48 ? ? 5.5 5.5 12.0 ?60 0.5 0.25 v v v v v v supply currents (all states, no loop current): i cca + i ccd (+5 v) iv sp (+10 v) i bat (?48 v) ? ? ? 4.9 45 ?3.1 7.0 200 ?4.0 ma a ma total power dissipation (all states, no loop current) (v cc = +5 v; v sp = +10 v; v bat = ?48 v) ?175200mw power supply rejection (tip/ring and transmit) ? : v cca (500 hz?3 khz; 50 mvrms ripple) v ccd (500 hz?3 khz; 50 mvrms ripple) v sp (500 hz?3 khz; 250 mvrms ripple) v bat (500 hz?3 khz; 50 mvrms ripple) 30 45 45 45 40 ? ? ? ? ? ? ? db db db db thermal ? : thermal resistance (still air) operating t jc ? ? ? ? 47 155 c/w c table 5. ring trip detector parameter min typ max unit voltage at input that will cause ring trip after appropriate zero crossings. 2.5 3 3.5 v voltage at input that will cause immediate ring trip. 12 15 18 v ringing source 1 : frequency (f) dc voltage ac voltage 19 ?39.5 60 20 ? ? 28 ?57 105 hz v vrms ring trip (ndet = 0) 2, 3 : loop resistance trip time ndet valid 2000 ? ? ? ? ? ? 200 80 ? ms ms
11 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics (continued) table 6. battery feed characteristics 1. the longitudinal current is independent of dc loop current. 2. current limit, i lim , is programmed by a resistor, r prog , from pin i prog to pin dc out . r prog = 1.667 x (i lim ? 4); r prog in k ? and i lim in ma. the current limit versus loop voltage has a slope of 10 k ? . the low current mode current limit is approximately 0.66 times the high current limit. the ground start ring lead ground current limit is approximately equal to the high current limit and has a slope of about 5 k ? . 3. in transmission applications, for compliance with tr-57, ground start ring lead i-v characteristics at high battery, it is e xpected that the high-current active current limit will be set to 28 ma. 4. loop closure detector current, i lcd , is programmed by a resistor, rlcth, from pin lcth to pin dc out . rlcth = 2.5 x i lcd ; rlcth in k ? and i lcd in ma. i lcd is the tip to ring (forward battery) or ring to tip (reverse battery) current at which the loop closure detector indicates an off-hook. 5. dc feed resistance may be adjusted between 180 ? and 600 ? using a resistor divider between dc out and dcr. the open loop differential voltage may also be increased by applying a negative voltage to pin dcr. see dc gains, pin dcr. 6. dc out gain depends on the resistor rgx1 from pin vitr to pin itr. this gain assumes 8250 ? , the recommended value. positive current is defined as the differential current flowing from pt to pr. 7. positive voltage on pin dcr has no effect on the pt/pr voltage. 8. at tip and ring, assuming 82.5 ? protection resistors. 9. at tip and ring with matched 82.5 ? protection resistors when feedback is connected for either 600 ? or 900 ? termination impedance. parameter symbol min typ max unit tip or ring drive current = dc + longitudinal + signal currents ?65 ? ?ma ac signal current ? 10 ? ? marms longitudinal current capability per wire 1 ?8.5 15 ?marms dc loop current limit 2 (r loop = 100 ? ): i lim programmability range 5 ? 45 ma current limit with v bat = ?51.5 v and r prog = 64.9 k ? 44 42 56 ma low-current mode 2 (r loop = 100 ?, v bat = ?51.5 v, and r prog = 64.9 k ? ) 25 27.5 30 ma ground start ring grounded (r loop = 100 ? ) current limit 3 : v bat = ?51.5 v, r prog = 64.9 k ? 38 43 47 ma loop closure current detector threshold 4 programming accuracy i lcd ??7% open loop voltages (dcr = 0 v): common-mode voltage differential voltage ? ? |v bat + 7.0| (v bat + 1.8)/2 |v bat + 6.5| ? |v bat + 6.0| v v disconnect state pt/pr voltage |pt-pr| ? ? 100 mv ground start ring lead open or shorted to ground: pt and cf1 voltage ? ?1.7 ?2.0 ?2.3 v dc feed resistance: dcr grounded dcr connected to dc out 5 ? 130 480 150 505 170 630 ? ? dc gains: pt/pr current to dc out voltage 6 : forward battery reverse battery dcr voltage 7 to pt/pr differential voltage ? ?118 118 3.13 ? ? 3.33 ?132 132 3.53 v/a v/a ? loop resistance range 8 (3.17 dbm overload into 600 ? ): i loop = 20 ma at v bat = ?51.5 v ? 1890 1930 ? ? longitudinal to metallic balance? ieee ? std. 455: 50 hz to 1 khz 1 khz to 3 khz ? 58 9 48 70 66 ? ? db db metallic to longitudinal (harm) balance: 200 hz to 4 khz ? 35 ? ? db
12 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics (continued) table 7. analog signal pins 1. this parameter is not tested in production; it is guaranteed by design and device characterization. 2. vtx offset is measured with respect to pin vrtx. 3. positive voltages from 0 v to v cca are permitted at input dcr; however, voltages above 0 v have no effect on either the dc feed resistance or tip/ ring voltage. parameter min typ max unit dc out : output offset (no loop current) output drive current output voltage swing (+0.25 ma/?3 ma load): maximum minimum output short-circuit current output load resistance output load capacitance 1 ? 0.25 v bat ?10 ? 5 ? ? ? ? ? ? ? ? 200 ?3.0 v cca 0.5 20 ? 50 mv ma v v ma k ? pf vitr and vtx: output offset (no loop current) 2 output drive current output voltage swing (1 ma load): maximum minimum (vitr) minimum (vtx) output short-circuit current output load resistance output load capacitance 1 ? 1 ?10 3.5 ?3.5 ? 4 ? ? ? ? ? ? ? ? ? 100 ? v cca ? v cca ? 1.0 20 ? 50 mv ma v v v ma k ? pf vrtx: output voltage output drive current output short-circuit current output load capacitance 1 2.2 500 ? ? 2.4 ? ? ? 2.6 ? 15 50 v a ma pf rsw: impedance to ground 3 ? ? m ? dcr: input voltage range 3 input bias current input impedance ?8 ? 500 ? ? ? 0 1 ? v a k ? txi: input impedance input voltage compliance input clamp voltage 75 0.4 0.4 ? ? ? ? ? 0.8 k ? v v rcvp and rcvn: input voltage range input bias current input impedance ?2.5 ? 10 ? ? ? v cca 1.5 ? v a m ? pt and pr: overvoltage (from external source; continuous) ? ? 265 v fb1 and fb2: ac output impedance output short-circuit current ? 27 ? ? 10 34 k ? a cf1 and cf2: output impedance 1 180 ? 375 k ?
13 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics (continued) transmit direction is tip/ring to vtx. receive direction is rcvp(n) to tip/ring. table 8. transmission characteristics 1. set by external components in conjunction with the t7531a/t7536 codecs. any complex impedance r1 + r2 || c between 200 ? and 1200 ? can be synthesized. 2. return loss and transhybrid loss are functions of device gain accuracies and the external hybrid circuit. guaranteed performa nce assumes 1% tolerance external resistors and capacitors. 3. this parameter is not tested in production; it is guaranteed by design and device characterization. 4. vtx gain depends on the resistor rgx1 from pin vitr to pin itr. this gain assumes an ideal 8250 ? , the recommended value. positive current is defined as the differential current flowing from pt to pr. the transmit signal at vtx is measured with respect to pin vrtx. parameter min typ max unit ac termination impedance 1 200 ? 1200 ? return loss 2 : 200 hz?500 hz 500 hz?3400 hz 25 29 ? ? ? ? db db total harmonic distortion (200 hz?4 khz) 3 : off-hook on-hook ? ? ? ? 0.3 1 % % transmit gain (f = 1 khz) 4 : pt/pr current to (vtx?vrtx) ?291 ?300 ?309 v/a receive gain (f = 1 khz): (rcvp?rcvn) to (pt?pr) 1.94 2 2.06 ? gain vs. frequency (transmit and receive) 3 (600 ? termination; 1 khz reference): 200 hz?300 hz 300 hz?3.4 khz 3.4 khz?20 khz 20 khz?266 khz ?0.3 ?0.05 ?3.0 ? 0 0 0 ? 0.05 0.05 0.05 2.0 db db db db gain vs. level (transmit and receive; 0 dbv reference) 3 : ?50 db to +3 db ?0.05 0 0.05 db transhybrid loss 2 : 200 hz?500 hz 500 hz?3400 hz 25 29 ? ? ? ? db db idle-channel noise (tip/ring; 600 ? termination): psophometric c-message 3 khz flat ? ? ? ? ? ? ?77 13 20 dbmp dbrnc dbrn idle-channel noise ((vtx?vrtx); 600 ? termination): psophometric c-message 3 khz flat ? ? ? ? ? ? ?77 13 20 dbmp0 dbrnc0 dbrn0 emc, per en 300 386-2 and en61000-4-6 (3 vrms, 80% modulation, 105 khz?80 mhz, 150 ? source impedance) 3 ? ? ?40 dbm, 600 ?
14 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics (continued) table 9. data interface and logic (logic inputs [clk, ncs, and b0?b5] and outputs [ndet]) 1. unless otherwise specified, all logic voltages are referenced to dgnd. 2. this parameter is not tested in production; it is guaranteed by design and device characterization. table 10. timing requirements (clk, b0?b5, and ncs) 1, 2 1. unless otherwise specified, all times are measured from the 50% point of logic transitions. 2. these parameters are not tested in production; they are guaranteed by design and device characterization. table 11. relay driver (rdo) 1. unless otherwise specified, all logic voltages are referenced to dgnd. 2. this parameter is not tested in production; it is guaranteed by design and device characterization. parameter 1 symbol min max unit high-level input voltage v ih 2v ccd v low-level input voltage v il 00.8v input bias current (high and low) i in ?10a high-level output voltage (i out = ?100 a) v oh v ccd ? 1.5 v ccd v low-level output voltage (i out = 180 a) v ol 00.4v output short-circuit current (v out = v ccd )i oss 135ma output load capacitance 2 c ol 050pf parameter symbol min max unit clk and ncs rise and fall time (10% to 90%) tr, tf 0 50 ns maximum input capacitance cin ? 5 pf minimum setup time from b0?b5 valid to ncs v ih = 2 v v ih = 2.5 v tsds tsds 250 150 ? ? ns ns minimum hold time from ncs to b0?b5 not valid v ih = 2 v v ih = 2.5 v thds thds 150 10 ? ? ns ns minimum pulse width of ncs twcs 195 ? ns clk frequency fclk 0.9 2.2 mhz minimum pulse width of clk twck 195 ? ns parameter 1 symbol min max unit off-state output current (v rdo = v ccd )i off ?10a on-state output voltage (i rdo = 40 ma) v on 00.60v on-state output voltage (i rdo = 20 ma) v on 00.40v clamp diode reverse current (v rdo = 0) i r ?10a clamp diode on voltage (i rdo = 80 ma) v oc 620v turn-on time 2 t on ?10s turn-off time 2 t off ?10s
15 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics (continued) table 12. ringing return access switch (sw1) 1. at 25 c, maximum voltage rating has a temperature coefficient of +0.167 v/c. 2. this parameter is not tested in production; it is guaranteed by design and device characterization. 3. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity at 200 v/s typical with no switch turn-on. in the case of dv/dt induced turn-on at higher dv/dt and amplitude, the design objective is no damage to at least 2000 v/s and full voltage. a known condition that can cause damage is initial current flow prior to the application of the dv/dt and the sudden application of reverse bias with dv/d t induced switch turn-off. in this case, no damage shall occur for dv/dt up to 2000 v/s as guaranteed by design and characterization. table 13. test-in access switches (sw3 and sw6) 1. at 25 c, maximum voltage rating has a temperature coefficient of +0.167 v/c. 2. this parameter is not tested in production; it is guaranteed by design and device characterization. 3. test in access switches current limit will be > tip and ring break switches current limit. 4. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity at 200 v/s typical with no switch turn-on. i n the case of dv/dt induced turn-on at higher dv/dt and amplitude, the design objective is no damage to at least 2000 v/s and full voltage. a known condition that can cause damage is initial current flow prior to the application of the dv/dt and the sudden application of reverse bias with dv/d t induced switch turn-off. in this case, no damage shall occur for dv/dt up to 2000 v/s as guaranteed by design and characterization. parameter min typ max unit off-state: maximum differential voltage dc leakage current (v sw = 320 v) feedthrough capacitance 2 ? ? ? ? ? ? 320 1 10 15 v a pf on-state (see on-state switch v-i characteristics section.): resistance (r on ) maximum differential voltage (v max ) foldback voltage breakpoint 1 (v 1 ) foldback voltage breakpoint 2 (v 2 ) current limit (i limit1 ) current limit (i limit2 ) ? ? 120 200 120 2 45 ? ? ? 220 ? 90 320 1 ? ? 360 ? ? v v v ma ma dv/dt sensitivity 2, 3 ? 200 2000 v/s parameter min typ max unit off-state: maximum differential voltage dc leakage current (v sw = 320 v) feedthrough capacitance 2 ? ? ? ? ? ? 320 1 10 15 v a pf on-state (see on-state switch v-i characteristics section.): resistance (r on ) maximum differential voltage (v max ) current limit (i limit ) switches sw3 and sw6 3 ? ? 85 45 ? ? 90 60 ? ? v ma dv/dt sensitivity 2, 4 ? 200 2000 v/s
16 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics (continued) table 14. tip and ring break switches (sw2 and sw4) 1. at 25 c, maximum voltage rating has a temperature coefficient of +0.167 v/c. 2. this parameter is not tested in production; it is guaranteed by design and device characterization. 3. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity at 200 v/s typical with no switch turn-on. in the case of dv/dt induced turn-on at higher dv/dt and amplitude, the design objective is no damage to at least 2000 v/s and full voltage. a known condition that can cause damage is initial current flow prior to the application of the dv/dt and the sudden application of reverse bias with dv/d t induced switch turn-off. in this case, no damage shall occur for dv/dt up to 2000 v/s as guaranteed by design and characterization. table 15. tip and ring feedback switches (sw2a and sw4a) 1. at 25 c, maximum voltage rating has a temperature coefficient of +0.167 v/c. 2. this parameter is not tested in production; it is guaranteed by design and device characterization. 3. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity at 200 v/s typical with no switch turn-on. i n the case of dv/dt induced turn-on at higher dv/dt and amplitude, the design objective is no damage to at least 2000 v/s and full voltage. a known condition that can cause damage is initial current flow prior to the application of the dv/dt and the sudden application of reverse bias with dv/d t induced switch turn-off. in this case, no damage shall occur for dv/dt up to 2000 v/s as guaranteed by design and characterization. parameter min typ max unit off-state: maximum differential voltage dc leakage current (v sw = 320 v) feedthrough capacitance 2 ? ? ? ? ? ? 320 1 20 50 v a pf on-state (see on-state switch v-i characteristics section.): resistance (r on ) maximum differential voltage (v max ) foldback voltage breakpoint 1 (v 1 ) foldback voltage breakpoint 2 (v 2 ) current limit (i limit1 ) current limit (i limit2 ) ? ? 60 v 1 + 0.5 85 2 25 ? ? ? 160 ? 50 320 1 ? ? 250 ? ? v v v ma ma dv/dt sensitivity 2, 3 ? 200 2000 v/s parameter min typ max unit off-state: maximum differential voltage dc leakage current (v sw = 320 v) feedthrough capacitance 2 ? ? ? ? ? ? 320 1 10 15 v a pf on-state (see on-state switch v-i characteristics section.): resistance (r on ) maximum differential voltage (v max ) current limit (i limit ) ? ? 0.5 4 ? ? 10 320 1 20 k ? v ma dv/dt sensitivity 2, 3 ? 200 2000 v/s
17 data sheet september 2001 l7585f full-feature, low-power slic and switch electrical characteristics (continued) table 16. ringing access switch (sw5) 1. this parameter is not tested in production; it is guaranteed by design and device characterization. 2. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity. 3. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity at 200 v/s typical with no switch turn-on. i n the case of dv/dt induced turn-on at higher dv/dt and amplitude, the design objective is no damage to at least 2000 v/s and full voltage. a known condition that can cause damage is initial current flow prior to the application of the dv/dt and the sudden application of reverse bias with dv/d t induced switch turn-off. in this case, no damage shall occur for dv/dt up to 2000 v/s as guaranteed by design and characterization. on-state switch i-v characteristics parameter min typ max unit off-state: maximum differential voltage dc leakage current (v sw = 500 v) dc leakage current (v sw = 250 v) feedthrough capacitance 1 ? ? ? ? ? ? ? 1 475 20 1 ? v a a pf on-state (see on-state switch v-i characteristics section.): crossover offset voltage (v os ; isw = 1 ma) resistance (r on ) surge current (10 s x 1000 s pulse) 1 release current 1 ? ? ? 0.1 ? ? ? ? 3 10 2.5 2 v ? a ma dv/dt sensitivity 1, 2 ? 200 2000 v/s common-mode voltage (maximum either switch terminal with re- spect to ground) ??320v 12-3291.a(f) a. sw2a, sw3, sw4a, sw6 12-3292.a(f) b. sw5 5-5990.c(f) c. sw1, sw2, sw4 figure 3. on-state switch i-v characteristics ?v max ?i limit +i limit +v max v sw +1.5 v ?1.5 v r on 2/3 r on current limiting i sw 2/3 r on current limiting ?v os +v os v sw r on i sw r on i lim1 i sw +1.5 2/3 r on r on ?1.5 ?i lim1 +v max v sw i lim2 ?i lim2 +v 2 +v 1 ?v max ?v 2 ?v 1
18 18 data sheet september 2001 l7585f full-feature, low-power slic and switch applications tip/ring protection the l7585 slic has integrated overvoltage tertiary protec- tion diodes in the tip and ring paths. the device also has an integrated thermal shutdown circuit which places tip/ring drivers in a high-impedance state when the die temperature exceeds 160 c. the slic requires the following to survive lightning and power cross requirements: fusible elements or ptcs current-limiting resistors a secondary protector thermal fuse/surge resistor modules that satisfy the various requirements can be purchased from mmc ? . protection resistors should have a tolerance of 1% and a ratio toler- ance of 0.5%. the suppressor breakover voltage of the sec- ondary protector should be set as low as possible. select a value just above the maximum peak ring signal and maxi- mum battery voltage. ndet under fault condition the state of ndet is not guaranteed with loss of battery. in the ringing state, rrng floating or with only dc on the ringing source, ndet will produce an off-hook because there are not zero crossings of ringing to cause an on- hook. in the ringing state with only ac (>40 vrms) on the ringing source, an on-hook will be produced after the second zero crossing of the ringing waveform, because there is no dc component to the ringing current. in the ringing state, if the resistor between rsw and pr is open, there will likely be a large voltage at the ringing input (due to capacitive loading) and ring trip will be asserted after the second zero crossing of ringing. because there is no guarantee of the load at pr in this condition, there can be no guarantee of the state on ndet in this condition. if the device enters into thermal shutdown due to a fault that causes an off-hook, the off-hook indication will be stable as the device cycles in and out of thermal shutdown. if the fault does not cause an off-hook, ndet will cycle between on- and off-hook as the device cycles in and out of thermal shutdown. power, clocking, and layout the slic requires +5 v (v cca and v ccd ) and a negative battery voltage (v bat ) to operate. the integrated switches require a 10 v or 12 v supply (v sp ) and a ttl clock (clk) to operate. clk requires a frequency between 1.0 mhz to 2.048 mhz with a 50% duty cycle. sw1, sw3, and sw6 will not operate without clk applied. a four- or six-layer board is recommended. analog and bat- tery grounds should be laid out as a plane and a layer, and tied together at the device. digital ground can also be tied to this plane or run separately. v sp is referenced to dgnd. v cc can be run as individual traces and can reside on the same layer as signal paths. v cca and v ccd can be tied together at the slic. placement of the talk battery is not critical. the ring bus should be on a separate layer from the slic/ codec interface signal leads and traces should run perpendic- ular if the traces must cross. txi, vitr, and itr are the sensitive nodes on the slic. transmit runners should be run in pairs, and receive runners should be run in pairs between the slic and the codec. a channel-to-channel spacing should be maintained.
19 data sheet september 2001 l7585f full-feature, low-power slic and switch applications (continued) ring trip ring trip is set by the value of rs1. the ring trip threshold at the ring trip inputs is 2.5 v mini- mum, 3.5 v maximum. a resistor value of 500 ? , as shown in figure 4, will set the ring trip current threshold to 6.0 ma typical. ring trip is asserted upon entering the ringing mode until the second zero crossing of ringing. this is either a positive- going zero crossing between ?40 v and ?30 v at ?50 v v bat ) or a negative-going zero crossing (between ?10 v and ?20 v at ?50 v v bat ). the different threshold for positive-going and negative-going zero cross- ings is the result of hysteresis of approximately 20 v. ring trip will not be asserted unless the ring trip threshold is exceeded for two zero crossings. this is either a positive- going zero crossing between ?40 v and ?30 v at ?50 v v bat ) or a negative-going zero crossing (between ?10 v and ?20 v at ?50 v v bat ). the different threshold for positive- going and negative-going zero crossings is the result of hys- teresis of approximately 20 v. note that since the ringing voltage is monitored at rsw, one zero crossing can occur at switch turn-on depending on ini- tial conditions. ring trip is asserted immediately if the ring trip input is 15 v 3 v. false on-hook transients if the l7585f is off-hook in the ground-start/tip open state, the ground-start/tip ground state, or the ground-start/tip amplifier state, due to an applied ring ground, and it is switched to the forward battery active state, it will not generate a false on-hook longer than 10 ms in duration. this applies for loop resistances of 0 ? to 2000 ?, providing that all of the following criteria are sat- isfied: ? a loop closure is applied before the l7585f switches to the forward battery active state. ? the loop closure resistance (telephone set) is less than 430 ? . ? the ring ground and loop closure are applied at the same end of the loop. ? if the ring ground is removed while the l7585f is in the forward battery active state, then the ring ground resistance must be greater than 225 ? when the dc cur- rent limit is 40 ma, or greater than 430 ? when the dc current is 28 ma.
20 data sheet september 2001 l7585f full-feature, low-power slic and switch application diagram 12-3351.r(f) * optional for quiet reverse battery. ? 4.096 mhz operation; for 2.048 mhz operation, tie scksel to v ss . figure 4. 16-channel line card solution osfs osck osdr0 osdr1 osdx0 osdx1 cdo cdi codec 0 t8532 dsp upck upcs updi updo sck sfs sdr sdx stsxb pcm codec 1 t8532 osdx2 osdr2 osdr3 osdx3 pcm interface control interface octal interface osdx2 osdr2 osdr3 osdx3 cdo cdi osck osfs osfs osck osdr0 osdr1 osdx0 osdx1 cdi cdo ccs0 ccs1 ccs0 ccs1 dgnd vccd rdo rsw rts pr pt rti tti clk vsp vbat bgnd vcca agnd ndet ncs b5 b4 b3 b2 b1 b0 fb1 fb2 cf1 cf2 dcr dcout iprog lcth rcvn rcvp vtx vrtx txi vitr itr relay k1 cvd 0.1 f crtf 0.1 f rs1 500 ? rrtf 1 m ? 260 v surge protector rpr 82.5 ? rpt 82.5 ? test-in bus 1 mhz clock battery back ringing cvb 0.1 f ?48 v cva 0.1 f +5 v +10 v fb2* cf1 0.22 f cf2 0.1 f rprog 64.9 k ? rlcth 24.9 k ? +5 v cb1 0.1 f slic 0 l7585 parallel data bus to microprocessor 0.1 f +5 v 0.1 f +5 v rstb scksel ? rstb 0.1 f0.1 f channels 8?15 channels 1?7 +5 v +5 v channel 0 vrn0 vrp0 vtx0 vrtx0 test test vddd rstb rstb rstb ck16 vss vssa 0.1 f +5 v 0.1 f vdd 2.4 v rgx1 8.25 k ? tip ring 0.047 f fb1* 0.047 f vdda vssa vddd vssd vdda vssa vddd vssd vdda micro- processor t8531a 100 v 100 v 100 v 100 v 10 v 50 v 100 v trng rrng earth back ringing trng rrng trng rrng ringing bus (see below) 100 v asic bus
21 data sheet september 2001 l7585f full-feature, low-power slic and switch outline diagram 44-pin plcc dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist your design efforts, please contact your agere communications sales representative. 5-2506(f)r7 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
data sheet september 2001 l7585f full-feature, low-power slic and switch legerity, inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liabilit y is assumed as a result of their use or application. copyright ? 2001 legerity, inc. all rights reserved september 2001 ds01-312alc (replaces ds00-216alc) ordering information ieee is a registered trademark of the institute of electrical and electronics engineers, inc. mmc is a trademark of microelectronic modules corporation. device part no. description package comcode lucl7585fp-d full-feature, low-power slic and switch 44-pin plcc (dry bag) 108417023 LUCL7585FP-DT full-feature, low-power slic and switch 44-pin plcc (tape and reel, dry bag) 108417031

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